The present invention relates to an error portion detecting method and layout method for a semiconductor integrated circuit, wherein a portion of the semiconductor integrated circuit which has a high possibility of error occurring due to a variation in the supply voltage during the operation carried out based on a clock signal, for example, is specified, whereby the specified vulnerable portion is countermeasured in a mask layout process.
In recent years, an effect of a voltage drop which may occur due to a power supply line has been increasing along with the increase in scale and the progress of miniaturization of semiconductor integrated circuits. That is, when the supply voltage is varied due to a voltage drop, the delay time or the signal level is also varied, and the possibility of a malfunction of a circuit increases.
Conventionally, for the purpose of preventing the above errors and malfunction, all of the design margins, such as a delay margin, and the like, have been increased, or the wire width for the power supply has been increased. However, such countermeasures make a design complicated or increase the number of gates and the chip area and accordingly increase the production cost.
In view of the above, there is a method which has been employed with more frequency wherein a variation in the supply voltage is calculated by simulating the operation of a circuit with consideration for the resistance and capacitance of wires, or the like, and the calculated voltage variation is fed back into the design and layout of a circuit. More specifically, in a known simulation technique, the voltage at a power supply terminal is calculated from, for example, the impedance value of the power supply line, the switching time information of a logic cell, and the current characteristics of the logic cell, and the delay time of the logic cell is calculated based on the calculated power supply terminal voltage to simulate the circuit operation (see, for example, Japanese Unexamined Patent Publication No. 7-239865).
However, in the case where the above simulation is carried out with high accuracy, a simulation apparatus requires abundant computer resources and an enormous length of time, and therefore, it is actually difficult to simulate the entire operation of a large-scale semiconductor integrated circuit with sufficient accuracy. Thus, it is difficult to build up a circuit design and layout design with quick and proper comprehension of the effect of a variation in the supply voltage.